PDSR (R5_ETM_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PDSR (R5_ETM_0) Register Description

Register NamePDSR
Offset Address0x0000000314
Absolute Address 0x00FEBFC314 (CORESIGHT_R5_ETM_0)
Width32
TyperwNormal read/write
Reset Value0x00000001
DescriptionPower-Down Status Register

PDSR (R5_ETM_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Sticky_reg 1rwNormal read/write0x0Sticky Register State. ETM-R5 does not support multiple power domains.
Powered_up 0rwNormal read/write0x1ETM Powered Up. The ETM Trace registers are accessible. ETM-R5 does not support multiple power domains.