PERFHPR1 (DDRC) Register Description
| Register Name | PERFHPR1 |
|---|---|
| Offset Address | 0x000000025C |
| Absolute Address | 0x00FD07025C (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x0F000001 |
| Description | High Priority Read CAM Register 1 |
This register is quasi-dynamic group 3. Group 3 registers can only be written when the controller is empty.
PERFHPR1 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| hpr_xact_run_length | 31:24 | rwNormal read/write | 0xF | Number of transactions that are serviced once the HPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. |
| hpr_max_starve | 15:0 | rwNormal read/write | 0x1 | Number of clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. |