PGCR0 (DDR_PHY) Register Description
| Register Name | PGCR0 |
|---|---|
| Offset Address | 0x0000000010 |
| Absolute Address | 0x00FD080010 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x07001E00 |
| Description | PHY General Configuration Register 0 |
PGCR0 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ADCP | 31 | rwNormal read/write | 0x0 | Address Copy: Enables, if set, the use of {RAS#,BA[2:0] and A[15:10]} as second copy of A[9:0]. This feature is valid only when design is in LPDDR3, LPDDR4 mode and these pins exist in the design. |
| Reserved | 30:27 | roRead-only | 0x0 | Reserved. Returns zeroes on reads. |
| PHYFRST | 26 | rwNormal read/write | 0x1 | AC loopback read FIFO reset: A write of 1b0 to this bit resets the AC Macro FIFOs (in both AC macros, if 2 AC macros are present) without resetting PUB RTL logic. This bit is not self-clearing and a 1b1 must be written to de-assert the reset. |
| OSCACDL | 25:24 | rwNormal read/write | 0x3 | Oscillator Mode Address/Command Delay Line Select: Selects which of the two address/command LCDLs is active. The delay select value of the inactive LCDL is set to zero while the delay select value of the active LCDL can be varied by the input write leveling delay select pin. Valid values are: 2b00 = No AC LCDL is active 2b01 = DDR AC LCDL is active 2b10 = CTL AC LCDL is active 2b11 = Both LCDLs are active |
| Reserved | 23:19 | roRead-only | 0x0 | Reserved. Returns zeroes on reads. |
| DTOSEL | 18:14 | rwNormal read/write | 0x0 | Digital Test Output Select: Selects the PHY digital test output that should be driven onto PHY digital test output (phy_dto) pin: Valid values are: 5b00000 = DATX8 0 PLL/PHY macro digital test output 5b00001 = DATX8 1 PLL/PHY macro digital test output 5b00010 = DATX8 2 PLL/PHY macro digital test output 5b00011 = DATX8 3 PLL/PHY macro digital test output 5b00100 = DATX8 4 PLL/PHY macro digital test output 5b00101 = DATX8 5 PLL/PHY macro digital test output 5b00110 = DATX8 6 PLL/PHY macro digital test output 5b00111 = DATX8 7 PLL/PHY macro digital test output 5b01000 = DATX8 8 PLL/PHY macro digital test output 5b01001 = AC PLL/PHY macro digital test output for AC Macro 0 5b01010 = AC PLL/PHY macro digital test output for AC Macro 1 5b01011 - 5b01111 = Reserved 5b10000 = DATX8 0 delay line digital test output 5b10001 = DATX8 1 delay line digital test output 5b10010 = DATX8 2 delay line digital test output 5b10011 = DATX8 3 delay line digital test output 5b10100 = DATX8 4 delay line digital test output 5b10101 = DATX8 5 delay line digital test output 5b10110 = DATX8 6 delay line digital test output 5b10111 = DATX8 7 delay line digital test output 5b11000 = DATX8 8 delay line digital test output 5b11001 = AC delay line digital test output for AC Macro 0 5b11010 = AC delay line digital test output for AC Macro 1 5b11011 - 5b11111 = Reserved NOTE: For DTO settings of 5b00000 to 5b01111, PGCR1.DTOMODE selects whether the digital test output is coming from the PLL or the PHY (AC/DATX8) macro |
| Reserved | 13 | roRead-only | 0x0 | Reserved. Returns zeroes on reads. |
| OSCDIV | 12:9 | rwNormal read/write | 0xF | Oscillator Mode Division: Specifies the factor by which the delay line oscillator mode output is divided down before it is output on the delay line digital test output pin dl_dto. Valid values are: 4b0000 = Divide by 1 4b0001 = Divide by 4 4b0010 = Divide by 8 4b0011 = Divide by 16 4b0100 = Divide by 32 4b0101 = Divide by 64 4b0110 = Divide by 128 4b0111 = Divide by 256 4b1000 = Divide by 512 4b1001 = Divide by 1024 4b1010 = Divide by 2048 4b1011 = Divide by 4096 4b1100 = Divide by 8192 4b1101 = Divide by 16384 4b1110 = Divide by 32768 4b 1111 = Divide by 65536 |
| OSCEN | 8 | rwNormal read/write | 0x0 | Oscillator Enable: Enables, if set, the delay line oscillation. |
| Reserved | 7:0 | roRead-only | 0x0 | Reserved. Returns zeroes on reads. |