PGCR4 (DDR_PHY) Register Description
| Register Name | PGCR4 |
|---|---|
| Offset Address | 0x0000000020 |
| Absolute Address | 0x00FD080020 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x001800C3 |
| Description | PHY General Configuration Register 4 |
PGCR4 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:30 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| ACDDLLD | 29 | rwNormal read/write | 0x0 | AC DDL Delay Select Dynamic Load: Specifies whether the registers inside the AC that hold the delay select signal of AC DDL should be dynamically loaded only when the delay select changes or should be continuously (always) loaded. This only applies to the AC delay LCDL. Valid values are: 1b0 = Delay select signal registers should be dynamically loaded only when the delay select signal has change and the delay load signal is high 1b1 = Delay select signal should be continuously (always) loaded on every clock cycle |
| ACDDLBYP | 28:24 | rwNormal read/write | 0x0 | AC DDL Bypass: Specifies, if set to 1b1 that the DDL delay should be bypassed. Otherwise the DDL bypass is turned off. Different bits control different AC DDLs as follows: ACDDLBYP [0] = CKN BDL delay bypass ACDDLBYP [1] = CK BDL delay bypass ACDDLBYP [2] = Address/command BDL delay bypass ACDDLBYP [3] = Address/command LCDL delay bypass ACDDLBYP [4] = Master delay line LCDL delay bypass |
| OEDDLBYP | 23 | rwNormal read/write | 0x0 | AC OE DDL Bypass: Specifies, if set to 1b1 that the DDL delay should be bypassed. Otherwise the DDL bypass is turned off |
| TEDDLBYP | 22 | rwNormal read/write | 0x0 | AC ODT DDL Bypass: Specifies, if set to 1b1 that the DDL delay should be bypassed. Otherwise the DDL bypass is turned off |
| PDRDDLBYP | 21 | rwNormal read/write | 0x0 | AC PDR DDL Bypass: Specifies, if set to 1b1 that the DDL delay should be bypassed. Otherwise the DDL bypass is turned off |
| RRRMODE | 20 | rwNormal read/write | 0x1 | AC Macro Read Path Rise-to-Rise Mode: Indicates if set that the PHY mission mode is configured to run in rise-to-rise mode for the read path. Otherwise if not set the PHY mission mode for the read path is running in rise-to-fall mode. |
| WRRMODE | 19 | rwNormal read/write | 0x1 | AC Macro Write Path Rise-to-Rise Mode: Indicates if set that the PHY mission mode is configured to run in rise-to-rise mode for the write path. Otherwise if not set the PHY mission mode for the write path is running in rise-to-fall mode. |
| Reserved | 18:8 | roRead-only | 0x0 | Returns zeros on Reads. |
| LPWAKEUP_THRSH | 7:4 | rwNormal read/write | 0xC | AC Low Power Wakeup Threshold: If dfi_lp_wakeup is greater than this threshold value, PLLs will be powered down when entering DFI low power mode. The value of the dfi_lp_wakeup signal at the time that the dfi_lp_ctrl_req or dfi_lp_data_req signal is asserted sets the tlp_wakeup time. Valid values in terms of number clock cycles are: 4b0000 = 16 cycles 4b0001 = 32 cycles 4b0010 = 64 cycles 4b0011 = 128 cycles 4b0100 = 256 cycles 4b0101 = 512 cycles 4b0110 = 1024 cycles 4b0111 = 2048 cycles 4b1000 = 4096 cycles 4b1001 = 8192 cycles 4b1010 = 16384 cycles 4b1011 = 32768 cycles 4b1100 = 65536 cycles 4b1101 = 131072 cycles 4b1110 = 262144 cycles 4b1111 = Unlimited cycles LPWAKEUP_THRSH calculation: MINIMUM LPWAKEUP CYCLES = pll_lock_time / ctl_clk_period + MDL calibration cycles where, MDL calibration cycles = N * DDL calibration cycles N is Decoded value of PGCR1.FDEPTH. Example, With tCK= 938 ps; ctl_clk = 1876 ps; and PGCR1.FDEPTH = 2b10: From the PGCR1 register description, FDEPTH=2b10 decodes to a depth of 8. Pll_lock_time from PLL spec is 25us. So LPWAKEUP_THRSH= 25 ns / 1876 ps + 8 * (800 cycles) = 13326 + 6400 = 19726 cycles Setting LPWAKEUP_THRSH to 4b1010 would trigger PLL power down for tlp_wakeup value of 32768 cycles and above; which meets the calculations for MINIMUM LPWAKEUP CYCLES of 19726 cycles |
| Reserved | 3:2 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| LPPLLPD | 1 | rwNormal read/write | 0x1 | AC Low Power PLL Power Down: Specifies if set that the PHY should respond to the DFI low power opportunity request and power down the PLL of the byte if the wakeup time request satisfies the LPWAKEUP_THRSH. LPWAKEUP_THRSH is the Minimum threshold value of tlp_wakeup required to make PHY go into low power mode by powering down PLL. The value of the dfi_lp_wakeup signal at the time that the dfi_lp_data_req&dfi_lp_ctrl_req signal is de-asserted sets the tlp_wakeup time. The value is in terms of number clock cycles. Refer Table 11 description of LPWAKEUP_THRSH for decoding details |
| LPIOPD | 0 | rwNormal read/write | 0x1 | AC Low Power I/O Power Down: Specifies if set that the PHY should respond to the DFI low power opportunity request and power down the I/Os of the byte. |