PGCR6 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PGCR6 (DDR_PHY) Register Description

Register NamePGCR6
Offset Address0x0000000028
Absolute Address 0x00FD080028 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00013000
DescriptionPHY General Configuration Register 6

PGCR6 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:24roRead-only0x0Returns zeroes on reads.
DLDLMT23:16rwNormal read/write0x1Delay Line VT Drift Limit: Specifies the minimum change in the delay line
VT drift in one direction which should result in the assertion of the delay
line VT drift status signal (vt_drift). The limit is specified in terms of delay
select values. A value of 0 disables the assertion of delay line VT drift
status signal.
Reserved15:14roRead-only0x0Returns zeroes on reads.
ACDLVT13rwNormal read/write0x1AC Address/Command Delay LCDL VT Compensation: Enables, if set,
the VT drift compensation of the address/command (ACD) LCDL.
ACBVT12rwNormal read/write0x1Address/Command Bit Delay VT Compensation: Enables, if set the VT
drift compensation of the address/command bit delay registers
ACBLDR1,2,6,7,8,9.
This bit doesn't control VT compensation for CK, CSN, CKE and ODT
BDLs.
ODTBVT11rwNormal read/write0x0ODT Bit Delay VT Compensation: Enables, if set the VT drift
compensation of the AC macro ODT bit delay registers ACBLDR4. The
VT compensation of ODT may produce a glitch on the SDRAM ODT and
should only be enabled if the SDRAM ODT is inactive.
CKEBVT10rwNormal read/write0x0CKE Bit Delay VT Compensation: Enables, if set the VT drift
compensation of the AC macro CKE bit delay registers ACBLDR5. The
VT compensation of CKE may produce a glitch on the SDRAM CKE and
should only be enabled if the SDRAM CKE is inactive.
CSNBVT 9rwNormal read/write0x0CSN Bit Delay VT Compensation: Enables, if set the VT drift
compensation of the AC macro CSN bit delay registers ACBLDR3. The
VT compensation of CSN may produce a glitch on the SDRAM CSN and
should only be enabled if the SDRAM CSN is inactive.
CKBVT 8rwNormal read/write0x0CK Bit Delay VT Compensation: Enables, if set the VT drift compensation
of the AC macro CK bit delay registers ACBLDR0. The VT compensation
of CK BDLs may produce a glitch on the SDRAM CK and should only be
enabled if the SDRAM CK is inactive.
Reserved 7:1roRead-only0x0Returns zeroes on reads.
INHVT 0rwNormal read/write0x0VT Calculation Inhibit: Inhibits calculation of the next VT compensated
delay line values. A value of 1 will initiate a stop of the VT compensation
logic. The bit PGSR1[30] (VSTOP) will be set to a logic x1 when VT
compensation has stopped. This bit should be set to 1 during writes to
the delay line registers. A value of 0 will re-enable the VT compensation
logic.