PGCR6 (DDR_PHY) Register Description
Register Name | PGCR6 |
---|---|
Offset Address | 0x0000000028 |
Absolute Address | 0x00FD080028 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00013000 |
Description | PHY General Configuration Register 6 |
PGCR6 (DDR_PHY) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:24 | roRead-only | 0x0 | Returns zeroes on reads. |
DLDLMT | 23:16 | rwNormal read/write | 0x1 | Delay Line VT Drift Limit: Specifies the minimum change in the delay line VT drift in one direction which should result in the assertion of the delay line VT drift status signal (vt_drift). The limit is specified in terms of delay select values. A value of 0 disables the assertion of delay line VT drift status signal. |
Reserved | 15:14 | roRead-only | 0x0 | Returns zeroes on reads. |
ACDLVT | 13 | rwNormal read/write | 0x1 | AC Address/Command Delay LCDL VT Compensation: Enables, if set, the VT drift compensation of the address/command (ACD) LCDL. |
ACBVT | 12 | rwNormal read/write | 0x1 | Address/Command Bit Delay VT Compensation: Enables, if set the VT drift compensation of the address/command bit delay registers ACBLDR1,2,6,7,8,9. This bit doesn't control VT compensation for CK, CSN, CKE and ODT BDLs. |
ODTBVT | 11 | rwNormal read/write | 0x0 | ODT Bit Delay VT Compensation: Enables, if set the VT drift compensation of the AC macro ODT bit delay registers ACBLDR4. The VT compensation of ODT may produce a glitch on the SDRAM ODT and should only be enabled if the SDRAM ODT is inactive. |
CKEBVT | 10 | rwNormal read/write | 0x0 | CKE Bit Delay VT Compensation: Enables, if set the VT drift compensation of the AC macro CKE bit delay registers ACBLDR5. The VT compensation of CKE may produce a glitch on the SDRAM CKE and should only be enabled if the SDRAM CKE is inactive. |
CSNBVT | 9 | rwNormal read/write | 0x0 | CSN Bit Delay VT Compensation: Enables, if set the VT drift compensation of the AC macro CSN bit delay registers ACBLDR3. The VT compensation of CSN may produce a glitch on the SDRAM CSN and should only be enabled if the SDRAM CSN is inactive. |
CKBVT | 8 | rwNormal read/write | 0x0 | CK Bit Delay VT Compensation: Enables, if set the VT drift compensation of the AC macro CK bit delay registers ACBLDR0. The VT compensation of CK BDLs may produce a glitch on the SDRAM CK and should only be enabled if the SDRAM CK is inactive. |
Reserved | 7:1 | roRead-only | 0x0 | Returns zeroes on reads. |
INHVT | 0 | rwNormal read/write | 0x0 | VT Calculation Inhibit: Inhibits calculation of the next VT compensated delay line values. A value of 1 will initiate a stop of the VT compensation logic. The bit PGSR1[30] (VSTOP) will be set to a logic x1 when VT compensation has stopped. This bit should be set to 1 during writes to the delay line registers. A value of 0 will re-enable the VT compensation logic. |