PGCR7 (DDR_PHY) Register Description
| Register Name | PGCR7 |
|---|---|
| Offset Address | 0x000000002C |
| Absolute Address | 0x00FD08002C (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | PHY General Configuration Register 7 |
PGCR7 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:8 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| ACRSVD_7_6 | 7:6 | rwNormal read/write | 0x0 | These bits are reserved for future AC special PHY modes but the registers are already connected to existing (unused) AC phy_mode bits. |
| ACCALCLK | 5 | rwNormal read/write | 0x0 | AC Calibration Clock Select: Valid values are: 1b0 = ddr_clk (x4 clock) is used for delay line calibration 1b1 = ctl_clk (x1 clock) is used for delay line calibration |
| ACRCLKMD | 4 | rwNormal read/write | 0x0 | AC read Clock Mode: Valid values are: 1b0 = Read clock (ctl_rd_clk) is generated from AC ctl_rd_clk pin 1b1 = Read clock (ctl_rd_clk) is generated from AC ctl_clk pin |
| ACDLDT | 3 | rwNormal read/write | 0x0 | AC DDL Load Type: Specifies how the delay select signal is applied to the AC delay lines. This is only applicable to DDLs that have their delay select signals pipelined, such address/command LCDL 1b0 = Apply the delay select signal to the delay line only when the delay select load signal is active and by first loading the delay select into the pipeline register 1b1 = Apply the delay select signal to the delay line directly, bypassing any pipeline registers and ignoring the delay select load signal |
| ACRSVD_2 | 2 | rwNormal read/write | 0x0 | This bit is reserved for future AC special PHY modes but the register is already connected to existing (unused) AC phy_mode bits. |
| ACDTOSEL | 1 | rwNormal read/write | 0x0 | AC Digital Test Output Select: This is used to select the AC internal signals that should be driven on the two AC digital test outputs (phy_status[1:0]) signals. Valid values for AC digital test output bit 0 (phy_status[0]) are: 1b0 = Reserved 1b1 = Controller delayed clock (after the LCDL delay) - ctl_dly_clk Valid values for digital test out bit 1[1] (phy_status[1]) are: 1b0 =Reserved 1b1 = DDR delayed clock (after the LCDL delay) -ddr_dly_clk |
| ACTMODE | 0 | rwNormal read/write | 0x0 | AC Test Mode: This is used to enable special test mode in the AC macro. Valid values are: 1b0 = Normal mode 1b1 = Test mode |