PGSR0 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2024-03-13

Revision

1.10

PGSR0 (DDR_PHY) Register Description

Register Name	PGSR0
Offset Address	0x0000000030
Absolute Address	0x00FD080030 (DDR_PHY)
Width	32
Type	roRead-only
Reset Value	0x00000000
Description	PHY General Status Register 0

PGSR0 (DDR_PHY) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
APLOCK	31	roRead-only	0x0	AC PLL Lock: Indicates, if set, that the AC PLL has locked. This is a direct status of the AC PLL lock pin. If DWC_DDRPHYAC_top.v does not contain a PLL (due to PLL sharing with a DATX8 or due to configuring the IP with all PLLs omitted), this bit will always remain 0.
CAWRN	29	roRead-only	0x0	CA Training Warning: Indicates if set that there is a warning in LPDDR3 CA training.
CAERR	28	roRead-only	0x0	CA Training Error: Indicates if set that there is an error in LPDDR3 CA training.
WEERR	27	roRead-only	0x0	Write Eye Training Error: Indicates if set that there is an error in write eye training.
REERR	26	roRead-only	0x0	Read Eye Training Error: Indicates if set that there is an error in read eye training.
WDERR	25	roRead-only	0x0	Write Bit Deskew Error: Indicates if set that there is an error in write bit deskew.
RDERR	24	roRead-only	0x0	Read Bit Deskew Error: Indicates if set that there is an error in read bit deskew.
WLAERR	23	roRead-only	0x0	Write Leveling Adjustment Error: Indicates if set that there is an error in write leveling adjustment.
QSGERR	22	roRead-only	0x0	DQS Gate Training Error: Indicates if set that there is an error in DQS gate training.
WLERR	21	roRead-only	0x0	Write Leveling Error: Indicates if set that there is an error in write leveling.
ZCERR	20	roRead-only	0x0	Impedance Calibration Error: Indicates if set that there is an error in impedance calibration.
VERR	19	roRead-only	0x0	VREF Training Error: Indicates if set that there is and error in VREF training.
DQS2DQERR	18	roRead-only	0x0	Write DQS2DQ Training Error: Indicates if set that there is an error in DQS2DQ training.
Reserved	17:16	roRead-only	0x0	Reserved. Returns zeroes on reads.
DQS2DQDONE	15	roRead-only	0x0	Write DQS2DQ Training done. Indicates if set that write DQS2DQ training has completed.
VDONE	14	roRead-only	0x0	VREF Training Done: Indicates if set that DRAM and Host VREF training has completed.
CADONE	12	roRead-only	0x0	CA Training Done: Indicates if set that LPDDR3 CA training has completed.
WEDONE	11	roRead-only	0x0	Write Eye Training Done: Indicates if set that write eye training has completed.
REDONE	10	roRead-only	0x0	Read Eye Training Done: Indicates if set that read eye training has completed.
WDDONE	9	roRead-only	0x0	Write Bit Deskew Done: Indicates if set that write bit deskew has completed.
RDDONE	8	roRead-only	0x0	Read Bit Deskew Done: Indicates if set that read bit deskew has completed.
WLADONE	7	roRead-only	0x0	Write Leveling Adjustment Done: Indicates if set that write leveling adjustment has completed.
QSGDONE	6	roRead-only	0x0	DQS Gate Training Done: Indicates if set that DQS gate training has completed.
WLDONE	5	roRead-only	0x0	Write Leveling Done: Indicates if set that write leveling has completed.
DIDONE	4	roRead-only	0x0	DRAM Initialization Done: Indicates if set that DRAM initialization has completed.
ZCDONE	3	roRead-only	0x0	Impedance Calibration Done: Indicates if set that impedance calibration has completed.
DCDONE	2	roRead-only	0x0	Digital Delay Line (DDL) Calibration Done: Indicates if set that DDL calibration has completed.
PLDONE	1	roRead-only	0x0	PLL Lock Done: Indicates if set that PLL locking has completed.
IDONE	0	roRead-only	0x0	Initialization Done: Indicates if set that the DDR system initialization has completed. This bit is set after all the selected initialization routines in PIR register have completed. Wait at least 32 ctl_clk cycles after this is first observed to be 1b1 before starting/resuming traffic to DRAM or triggering new PIR.INIT.