PGSR1 (DDR_PHY) Register Description
Register Name | PGSR1 |
---|---|
Offset Address | 0x0000000034 |
Absolute Address | 0x00FD080034 (DDR_PHY) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | PHY General Status Register 1 |
PGSR1 (DDR_PHY) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
PARERR | 31 | roRead-only | 0x0 | RDIMM Parity Error: Indicates, if set, that there was a parity error (i.e. err_out_n was sampled low) during one of the transactions to the RDIMM buffer chip. This bit remains asserted until cleared by the PIR.CLRSR. |
VTSTOP | 30 | roRead-only | 0x0 | VT Stop: Indicates if set that the VT calculation logic has stopped computing the next values for the VT compensated delay line values. After assertion of the PGCR.INHVT, the VTSTOP bit should be read to ensure all VT compensation logic has stopped computations before writing to the delay line registers. |
Reserved | 29:25 | roRead-only | 0x0 | Reserved. Returns zeroes on reads. |
DLTCODE | 24:1 | roRead-only | 0x0 | Delay Line Test Code for AC macro 0: Returns the code measured by the PHY control block that corresponds to the period of the AC delay line digital test output. |
DLTDONE | 0 | roRead-only | 0x0 | Delay Line Test Done for AC macro 0: Indicates, if set, that the PHY control block has finished doing period measurement of the AC delay line digital test output. |