PGSR1 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PGSR1 (DDR_PHY) Register Description

Register NamePGSR1
Offset Address0x0000000034
Absolute Address 0x00FD080034 (DDR_PHY)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionPHY General Status Register 1

PGSR1 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PARERR31roRead-only0x0RDIMM Parity Error: Indicates, if set, that there was a parity error (i.e.
err_out_n was sampled low) during one of the transactions to the RDIMM
buffer chip. This bit remains asserted until cleared by the PIR.CLRSR.
VTSTOP30roRead-only0x0VT Stop: Indicates if set that the VT calculation logic has stopped
computing the next values for the VT compensated delay line values. After
assertion of the PGCR.INHVT, the VTSTOP bit should be read to ensure
all VT compensation logic has stopped computations before writing to the
delay line registers.
Reserved29:25roRead-only0x0Reserved. Returns zeroes on reads.
DLTCODE24:1roRead-only0x0Delay Line Test Code for AC macro 0: Returns the code measured by the
PHY control block that corresponds to the period of the AC delay line
digital test output.
DLTDONE 0roRead-only0x0Delay Line Test Done for AC macro 0: Indicates, if set, that the PHY
control block has finished doing period measurement of the AC delay line
digital test output.