PIDR0 (FTM) Register Description
| Register Name | PIDR0 |
|---|---|
| Offset Address | 0x0000000FE0 |
| Absolute Address | 0x00FE9D0FE0 (CORESIGHT_SOC_FTM) |
| Width | 8 |
| Type | roRead-only |
| Reset Value | 0x00000021 |
| Description | Peripheral ID0 |
PIDR0 (FTM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ID | 7:0 | roRead-only | 0x21 | [7:0] is Part Number [7:0] (from Xilinx family[2:0] + subfamily[3:0] + device_code[4]) |