PIDR2 (R5_DBG_0) Register Description
| Register Name | PIDR2 |
|---|---|
| Offset Address | 0x0000000FE8 |
| Absolute Address | 0x00FEBF0FE8 (CORESIGHT_R5_DBG_0) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x0000004B |
| Description | Peripheral ID Register 2 |
PIDR2 (R5_DBG_0) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| REVISION | 7:4 | roRead-only | 0x4 | Indicates the revision number for the Cortex-R5 processor. This is the major revision number nin the rn part of the rnpn description of the product revision status. |
| JEDEC | 3 | roRead-only | 0x1 | Indicates that the processor uses a JEP 106 identity code. |
| DES_1 | 2:0 | roRead-only | 0x3 | Indicates bits [6:4] of the JEDEC JEP106 Identity Code. |