PIDR4 (TPIU) Register Description
| Register Name | PIDR4 |
|---|---|
| Offset Address | 0x0000000FD0 |
| Absolute Address | 0x00FE980FD0 (CORESIGHT_SOC_TPIU) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Part of the set of Peripheral Identification registers. Contains part of the designer identity and the memory footprint indicator. |
PIDR4 (TPIU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| SIZE | 7:4 | roRead-only | 0x0 | This is a 4-bit value that indicates the total contiguous size of the memory window used by this component in powers of 2 from the standard 4KB. If a component only requires the standard 4KB then this should read as 0x0, 4KB only, for 8KB set to 0x1, 16KB == 0x2, 32KB == 0x3, and so on. |
| DES_2 | 3:0 | roRead-only | 0x0 | JEDEC continuation code indicating the designer of the component (along with the identity code) |