PIR (DDR_PHY) Register Description
| Register Name | PIR |
|---|---|
| Offset Address | 0x0000000004 |
| Absolute Address | 0x00FD080004 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | PHY Initialization Register |
PIR (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31 | roRead-only | 0x0 | Return zeroes on reads. |
| ZCALBYP | 30 | wtcReadable, write a 1 to clear | 0x0 | Impedance Calibration Bypass: Bypasses or stops, if set, impedance calibration of all ZQ control blocks that automatically triggers after reset. Impedance calibration may be triggered manually using INIT and ZCAL bits of the PIR register. This bit is self-clearing. Note: The impedance calibration is stopped immediately. However, DFI control/PHY update requests will continue to be processed. ZCTRL override does not work in this mode. |
| DCALPSE | 29 | wtcReadable, write a 1 to clear | 0x0 | Digital Delay Line (DDL) Calibration Pause: Pauses or halts, if set, DDL calibration. Clearing this bit will restart DDL calibrations. DDL calibration may be triggered manually using INIT and DCAL bits of the PIR register. This bit should be set to 0 during DFI low power operation. |
| Reserved | 28:21 | roRead-only | 0x0 | Return zeroes on reads. |
| DQS2DQ | 20 | rwNormal read/write | 0x0 | Write DQS2DQ training: Executes a PUB training routine that compensates the clock tree delay (tDQS2DQ) in memory devices |
| RDIMMINIT | 19 | rwNormal read/write | 0x0 | RDIMM Initialization: Executes the RDIMM buffer chip initialization before executing DRAM initialization. The RDIMM buffer chip initialization is run after the DRAM is reset and CKE have been driven high by the DRAM initialization sequence |
| CTLDINIT | 18 | rwNormal read/write | 0x0 | Controller DRAM Initialization: Indicates if set that DRAM initialization will be performed by the controller. Otherwise if not set it indicates that DRAM initialization will be performed using the built-in initialization sequence or using software through the configuration port. |
| VREF | 17 | rwNormal read/write | 0x0 | VREF training: Executes a PUB training routine for DRAM and HOST DQ I/O VREF values to enhance the write and read eye position. |
| WREYE | 15 | rwNormal read/write | 0x0 | Write Data Eye Training: Executes a PUB training routine to maximize the write data eye. |
| RDEYE | 14 | rwNormal read/write | 0x0 | Read Data Eye Training: Executes a PUB training routine to maximize the read data eye. |
| WRDSKW | 13 | rwNormal read/write | 0x0 | Write Data Bit Deskew: Executes a PUB training routine to deskew the DQ bits during write. |
| RDDSKW | 12 | rwNormal read/write | 0x0 | Read Data Bit Deskew: Executes a PUB training routine to deskew the DQ bits during read. |
| WLADJ | 11 | rwNormal read/write | 0x0 | Write Leveling Adjust: Executes a PUB training routine that re-adjusts the write latency used during write in case the write leveling routine changed the expected latency. |
| QSGATE | 10 | rwNormal read/write | 0x0 | Read DQS Gate Training: Executes a PUB training routine to determine the optimum position of the read data DQS strobe for maximum system timing margins. |
| WL | 9 | rwNormal read/write | 0x0 | Write Leveling: Executes a PUB write leveling routine. |
| DRAMINIT | 8 | rwNormal read/write | 0x0 | DRAM Initialization: Executes the DRAM initialization sequence. |
| DRAMRST | 7 | rwNormal read/write | 0x0 | DRAM Reset Issues a reset to the DRAM (by driving the DRAM reset pin low) and wait 200us. This can be triggered in isolation or with the full DRAM initialization (DRAMINIT). For the later case, the reset is issued and 200us is waited before starting the full initialization sequence. Note: DDR4 and DDR3 only |
| PHYRST | 6 | rwNormal read/write | 0x0 | PHY Reset: Resets the AC and DATX8 modules by asserting the AC/DATX8 reset pin. |
| DCAL | 5 | rwNormal read/write | 0x0 | Digital Delay Line (DDL) Calibration: Performs PHY delay line calibration. If maintaining valid DRAM data and state through this calibration is required, then the DRAM should be put into self refresh before setting this bit to trigger the calibration; the use must also remove DRAM from self refresh after the calibration is completed before accessing the DRAM. |
| PLLINIT | 4 | rwNormal read/write | 0x0 | PLL Initialization: Executes the PLL initialization sequence which includes correct driving of PLL power-down, reset and gear shift pins, and then waiting for the PHY PLLs to lock. |
| Reserved | 3 | roRead-only | 0x0 | Return zeroes on reads. |
| CA | 2 | rwNormal read/write | 0x0 | CA Training: Performs PHY LPDDR3 CA training. When set theLPDDR3 CA training will be performed after with PHY initialization (PLL initialization + DDL calibration + PHY reset). |
| ZCAL | 1 | rwNormal read/write | 0x0 | Impedance Calibration: Executes impedance calibration |
| INIT | 0 | wtcReadable, write a 1 to clear | 0x0 | Initialization Trigger: A write of 1b1 to this bit triggers the DDR system initialization, including PHY initialization, DRAM initialization, and PHY training. The exact initialization steps to be executed are specified in bits 1 to 15 of this register. A bit setting of 1 means the step will be executed as part of the initialization sequence, while a setting of 1b0 means the step will be bypassed. The initialization trigger bit is self-clearing. It is recommended that this bit be set 1b1 in a separate config write step after other bits in this register have been programmed to avoid any race condition. The PGSR0.IDONE status bit indicates when the initialization steps are complete. Wait at least 32 ctl_clk cycles after PGSR0.IDONE is observed to be 1b1 before starting or resuming traffic to DRAM. Caution: This bit should be set to 1b1 to trigger the DDR system initialization only when the DDR/DFI interfaces are idle and DFI update interface is disabled in Controller as well as in PHY (DSGCR.PUREN=0). Note: Controller/Software must ensure that all DRAM timings have been met for all prior issued commands before triggering any PUB Mode operation. |