PL2_THR_CTRL (CRL_APB) Register Description
Register Name | PL2_THR_CTRL |
---|---|
Offset Address | 0x00000000E0 |
Absolute Address | 0x00FF5E00E0 (CRL_APB) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000001 |
Description | PL Clock 2 Threshold Control and status |
PL2_THR_CTRL (CRL_APB) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
CURR_VAL | 31:16 | roRead-only | 0x0 | Current clock value as it counts down to 0. Valid when the [RUNNING] bit = 0, undefined when [RUNNING] = 1. |
RUNNING | 15 | roRead-only | 0x0 | Counter Status. 0: not running. 1: running. |
Reserved | 14:2 | rwNormal read/write | 0x0 | reserved |
CPU_START | 1 | rwNormal read/write | 0x0 | Start counting. Prerequisite: program the count into PLx_THR_CNT [LAST_CNT]. |
CNT_RST | 0 | rwNormal read/write | 0x1 | Reset internal counter. 0: run. 1: held in reset. |