PLL_STATUS (CRL_APB) Register Description
Register Name | PLL_STATUS |
---|---|
Offset Address | 0x0000000040 |
Absolute Address | 0x00FF5E0040 (CRL_APB) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000018 |
Description | LPD PLL Clocking Status. |
PLL_STATUS (CRL_APB) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:6 | rwNormal read/write | 0x0 | reserved |
RPLL_STABLE | 4 | roRead-only | 0x1 | RPLL stability status. 0: not locked or bypassed. 1: locked or bypassed. |
IOPLL_STABLE | 3 | roRead-only | 0x1 | IOPLL stability status. 0: not locked or bypassed. 1: locked or bypassed. |
Reserved | 2 | rwNormal read/write | 0x0 | reserved |
RPLL_LOCK | 1 | roRead-only | 0x0 | RPLL lock status. 0: not locked. 1: locked. |
IOPLL_LOCK | 0 | roRead-only | 0x0 | IOPLL lock status. 0: not locked. 1: locked. |