| Field Name | Bits | Type | Reset Value | Description |
|---|
| rd_poison_intr_5 | 21 | roRead-only | 0x0 | Read transaction poisoning error interrupt on input for port 5. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI ports read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. |
| rd_poison_intr_4 | 20 | roRead-only | 0x0 | Read transaction poisoning error interrupt on input for port 4. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI ports read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. |
| rd_poison_intr_3 | 19 | roRead-only | 0x0 | Read transaction poisoning error interrupt on input for port 3. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI ports read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. |
| rd_poison_intr_2 | 18 | roRead-only | 0x0 | Read transaction poisoning error interrupt on input for port 2. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI ports read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. |
| rd_poison_intr_1 | 17 | roRead-only | 0x0 | Read transaction poisoning error interrupt on input for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI ports read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. |
| rd_poison_intr_0 | 16 | roRead-only | 0x0 | Read transaction poisoning error interrupt on input for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI ports read address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. |
| wr_poison_intr_5 | 5 | roRead-only | 0x0 | Write transaction poisoning error interrupt on input for port 5. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI ports write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. |
| wr_poison_intr_4 | 4 | roRead-only | 0x0 | Write transaction poisoning error interrupt on input for port 4. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI ports write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. |
| wr_poison_intr_3 | 3 | roRead-only | 0x0 | Write transaction poisoning error interrupt on input for port 3. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI ports write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. |
| wr_poison_intr_2 | 2 | roRead-only | 0x0 | Write transaction poisoning error interrupt on input for port 2. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI ports write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. |
| wr_poison_intr_1 | 1 | roRead-only | 0x0 | Write transaction poisoning error interrupt on input for port 1. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI ports write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. |
| wr_poison_intr_0 | 0 | roRead-only | 0x0 | Write transaction poisoning error interrupt on input for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI ports write address channel. Bit 0 corresponds to Port 0, and so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. |