PRCR (R5_DBG_0) Register Description
| Register Name | PRCR |
|---|---|
| Offset Address | 0x0000000310 |
| Absolute Address | 0x00FEBF0310 (CORESIGHT_R5_DBG_0) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Device Powerdown and Reset Control Register |
PRCR (R5_DBG_0) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Hold_internal_reset | 2 | rwNormal read/write | 0x0 | Hold internal reset bit. This bit can be used to prevent the processor from running again before the debugger detects a power-down event and restoresthe state of the debug registers in the processor. This bit does not have any effect on initial system power-up, because nSYSPORESETclears it. 0 = Do not hold internal reset on power-up or warm reset. 1 = Hold the processor non-debug logic in reset on warm reset until this flag is cleared. |
| Force_internal_reset | 1 | rwNormal read/write | 0x0 | When a 1 is written to this bit, the processor asserts the DBGRSTREQm output for four cycles. You can connect this output to an external reset controller that, in turn, resets the processor. |
| No_power_down | 0 | rwNormal read/write | 0x0 | When set to 1, the DBGNOPWRDWN output signal is HIGH. This outputconnects to the system power controller and is interpreted as a request to operate in emulate mode, if the system supports this functionality. In this mode, the processor is not actually powered down when requested by software or hardware handshakes. This mode is useful when debugging applications on top of working operating systems. 0 = DBGNOPWRDWN is LOW. 1 = DBGNOPWRDWN is HIGH. |