PRSR (R5_DBG_1) Register Description
| Register Name | PRSR |
|---|---|
| Offset Address | 0x0000000314 |
| Absolute Address | 0x00FEBF2314 (CORESIGHT_R5_DBG_1) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Device Powerdown and Reset Status Register |
PRSR (R5_DBG_1) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Sticky_reset_status | 3 | rwNormal read/write | 0x0 | Sticky reset status bit. Thisbit is cleared on read. 0 = the processor has not been reset since the last time this register was read. 1 = the processor has been reset since the last time this register was read. This sticky bit is set to 1 when nRESETm is asserted. This bit is reset to 0 by PRESETDBGmn. |
| Reset_status | 2 | rwNormal read/write | 0 | Reset status bit: 0 = the processor is not held in reset 1 = the processor isheld in reset. This bit reads 1 when nRESETm is asserted. |
| Sticky_power_down_status | 1 | rwNormal read/write | 0x0 | Indicates if the core power domain has been powered down since the PRCR was last read. 0 = the CPU has not been powered down since the last read. 1 = the CPU has been powered down since the last read. If this bit is 1: . The contents of the core domain debug registers have been lost and must be reprogrammed. . Debug-APB transactions that access core domain debug registers receive an error response. This bit is cleared to 0 on a read. |
| Power_down_status | 0 | rwNormal read/write | 0 | Indicates the status of the core power domain: 0 = the CPU is powered-down, that is, it is in Dormant or Shutdown mode. Core-domain debug registers cannot be accessed. 1 = the CPU is powered-up, that is, it is in Run or Standby mode. All debug registers can be accessed. |