PSCR (ETF8K) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PSCR (ETF8K) Register Description

Register NamePSCR
Offset Address0x0000000308
Absolute Address 0x00FE950308 (CORESIGHT_SOC_ETF_2)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionThis register determines the reload value of the Periodic Synchronization Counter. This counter enables the frequency of synchronization information to be optimized to the trace capture buffer size.When the TMC is enabled, the Periodic Synchronization counter counts the number of bytes of trace data stored into the trace memory (regardless of whether the trace data has been formatted by the TMC or not) since the occurrence of the last synchronization request on the ATB slave interface. The value programmed into this register determines the reload value of the Periodic Synchronization counter.This counter is enabled only when the TraceCaptEn bit in the Control Register, CTL, 0x020, is set. Writing to this register other than when TraceCaptEn=0 and TMCReady=1 will result in Unpredictable behavior.

PSCR (ETF8K) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PSCount 4:0rwNormal read/write0x0Determines the reload value of the Synchronization Counter. The reload value takes effect the next time the counter reaches 0. Reads from this register return the reload value programmed into this register. This register is set to 0xA on reset, corresponding to a synchronization period of 1024 bytes.0x0: Synchronization disabled. 0x1-0x6: Reserved/UNP.0x7-0x1B: Synchronisation period is 2**PSCount bytes. For example, a value of 0x7 gives a synchronization period of 128 bytes.0x1C-0x1F: Reserved/UNP.