PTR0 (DDR_PHY) Register Description
| Register Name | PTR0 |
|---|---|
| Offset Address | 0x0000000040 |
| Absolute Address | 0x00FD080040 (DDR_PHY) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x42C21590 |
| Description | PHY Timing Register 0 |
PTR0 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| tPLLPD | 31:21 | rwNormal read/write | 0x216 | PLL Power-Down Time: Number of ctl_clk cycles that the PLL must remain in power-down mode, i.e. number of clock cycles from when PLL power-down pin is asserted to when PLL power-down pin is de-asserted. This must correspond to a value that is equal to or more than 1us. Default value corresponds to 1us. |
| tPLLGS | 20:6 | rwNormal read/write | 0x856 | PLL Gear Shift Time: Number of ctl_clk cycles from when the PLL reset pin is de-asserted to when the PLL gear shift pin is de-asserted. This must correspond to a value that is equal to or more than 4us. Default value corresponds to 4us. |
| tPHYRST | 5:0 | rwNormal read/write | 0x10 | PHY Reset Time: Number of ctl_clk cycles that the PHY reset must remain asserted after PHY calibration is done before the reset to the PHY is de-asserted. This is used to extend the reset to the PHY so that the reset is asserted for some clock cycles after the clocks are stable. Valid values are 5'd1-5'd63. |