PTR1 (DDR_PHY) Register Description
| Register Name | PTR1 |
|---|---|
| Offset Address | 0x0000000044 |
| Absolute Address | 0x00FD080044 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0xD05612C0 |
| Description | PHY Timing Register 1 |
PTR1 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| tPLLLOCK | 31:16 | rwNormal read/write | 0xD056 | PLL Lock Time: Number of ctl_clk cycles for the PLL to stabilize and lock, i.e. number of clock cycles from when the PLL reset pin is de-asserted to when the PLL has lock and is ready for use. The default value, 0d53334, is set for 100uS at CTL_CLK = 533 MHz and may be changed to a value that meets, or exceeds, the PLL Lock time, Tlock = 25us. |
| Reserved | 15:13 | roRead-only | 0x0 | Returns zeroes on reads. |
| tPLLRST | 12:0 | rwNormal read/write | 0x12C0 | PLL Reset Time: Number of ctl_clk cycles that the PLL must remain in reset mode, i.e. number of clock cycles from when PLL power-down pin is de-asserted and PLL reset pin is asserted to when PLL reset pin is de- asserted. This must correspond to a value that is equal to or more than 9us. Default value corresponds to 9us. |