PTR2 (DDR_PHY) Register Description
| Register Name | PTR2 |
|---|---|
| Offset Address | 0x0000000048 |
| Absolute Address | 0x00FD080048 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00083DEF |
| Description | PHY Timing Register 2 |
PTR2 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:20 | roRead-only | 0x0 | Return zeroes on reads. |
| tWLDLYS | 19:15 | rwNormal read/write | 0x10 | Write Leveling Delay Settling Time: Number of controller clock cycles from when a new value of the write leveling delay is applies to the LCDL to when to DQS high is driven high. |
| tCALH | 14:10 | rwNormal read/write | 0xF | Calibration Hold Time: Number of controller clock cycles from when the clock was disabled (cal_clk_en de-asserted) to when calibration is enable (cal_en asserted). The default value is the recommended minimum value. |
| tCALS | 9:5 | rwNormal read/write | 0xF | Calibration Setup Time: Number of controller clock cycles from when calibration is enabled (cal_en asserted) to when the calibration clock is asserted again (cal_clk_en asserted).). The default value is the recommended minimum value. |
| tCALON | 4:0 | rwNormal read/write | 0xF | Calibration On Time: Number of controller clock cycles that the calibration clock is enabled (cal_clk_en asserted). The default value is the recommended minimum value. |