PTR4 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PTR4 (DDR_PHY) Register Description

Register NamePTR4
Offset Address0x0000000050
Absolute Address 0x00FD080050 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x000010AA
DescriptionPHY Timing Register 4

PTR4 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:13roRead-only0x0Return zeroes on reads.
tDINIT112:0rwNormal read/write0x10AADRAM Initialization Time 1: DRAM initialization time in DRAM clock
cycles corresponding to the following:
DDR4 = CKE high time to first command (max (5nCK,tRFC(min) +
10ns) )
DDR3 = CKE high time to first command (tRFC + 10 ns or 5 tCK,
whichever is bigger)
LPDDR4= CKE high time to first command (2000 ns)
LPDDR3 = CKE low time with power and clock stable (100 ns)
Note:
Default value corresponds to LPDDR4 2000ns at 2133 MHz.