PTR4 (DDR_PHY) Register Description
Register Name | PTR4 |
---|---|
Offset Address | 0x0000000050 |
Absolute Address | 0x00FD080050 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x000010AA |
Description | PHY Timing Register 4 |
PTR4 (DDR_PHY) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:13 | roRead-only | 0x0 | Return zeroes on reads. |
tDINIT1 | 12:0 | rwNormal read/write | 0x10AA | DRAM Initialization Time 1: DRAM initialization time in DRAM clock cycles corresponding to the following: DDR4 = CKE high time to first command (max (5nCK,tRFC(min) + 10ns) ) DDR3 = CKE high time to first command (tRFC + 10 ns or 5 tCK, whichever is bigger) LPDDR4= CKE high time to first command (2000 ns) LPDDR3 = CKE low time with power and clock stable (100 ns) Note: Default value corresponds to LPDDR4 2000ns at 2133 MHz. |