PTR5 (DDR_PHY) Register Description
| Register Name | PTR5 |
|---|---|
| Offset Address | 0x0000000054 |
| Absolute Address | 0x00FD080054 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00068268 |
| Description | PHY Timing Register 5 |
PTR5 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:19 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| tDINIT2 | 18:0 | rwNormal read/write | 0x68268 | DRAM Initialization Time 2: DRAM initialization time in DRAM clock cycles corresponding to the following: DDR4 = Reset low time (200 us on power-up or 100 ns after power- up) DDR3 = Reset low time (200 us on power-up or 100 ns after power- up) LPDDR4 = Reset low time (200 us on power-up or 100 ns after power-up) LPDDR3 = Time from reset command to end of auto initialization (11 us) Default value corresponds to LPDDR4 200 us at 2133 MHz. |