PTR6 (DDR_PHY) Register Description
Register Name | PTR6 |
---|---|
Offset Address | 0x0000000058 |
Absolute Address | 0x00FD080058 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x04000855 |
Description | PHY Timing Register 6 |
PTR6 (DDR_PHY) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:27 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
tDINIT4 | 26:20 | rwNormal read/write | 0x40 | DRAM Initialization Time 4: DRAM initialization time in DRAM clock cycles corresponding to the following: LPDDR4 = Time from ZQCAL LATCH command to first command (tZQLAT= MAX(30ns,8 tCK)). Note: The default value corresponds to 8 tCK. |
Reserved | 19:12 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
tDINIT3 | 11:0 | rwNormal read/write | 0x855 | DRAM Initialization Time 3: DRAM initialization time in DRAM clock cycles corresponding to the following: DDR4 = Time from ZQ initialization command to first command (1 us) DDR3 = Time from ZQ initialization command to first command (1 us) LPDDR4 = Time from ZQCAL START command to ZQCAL LATCH command (tZQCAL=1 us) LPDDR3 = Time from ZQ initialization command to first command (1us) Note: Default value corresponds to LPDDR4 1us at 2133 Mbps. |