PTR6 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PTR6 (DDR_PHY) Register Description

Register NamePTR6
Offset Address0x0000000058
Absolute Address 0x00FD080058 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x04000855
DescriptionPHY Timing Register 6

PTR6 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:27roRead-only0x0Reserved. Return zeroes on reads.
tDINIT426:20rwNormal read/write0x40DRAM Initialization Time 4: DRAM initialization time in DRAM clock
cycles corresponding to the following:
LPDDR4 = Time from ZQCAL LATCH command to first command
(tZQLAT= MAX(30ns,8 tCK)).
Note: The default value corresponds to 8 tCK.
Reserved19:12roRead-only0x0Reserved. Return zeroes on reads.
tDINIT311:0rwNormal read/write0x855DRAM Initialization Time 3: DRAM initialization time in DRAM clock
cycles corresponding to the following:
DDR4 = Time from ZQ initialization command to first command (1 us)
DDR3 = Time from ZQ initialization command to first command (1 us)
LPDDR4 = Time from ZQCAL START command to ZQCAL LATCH
command (tZQCAL=1 us)
LPDDR3 = Time from ZQ initialization command to first command (1us)
Note: Default value corresponds to LPDDR4 1us at 2133 Mbps.