PWRCTL (APU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PWRCTL (APU) Register Description

Register NamePWRCTL
Offset Address0x0000000090
Absolute Address 0x00FD5C0090 (APU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPower Control Register

PWRCTL (APU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CLREXMONREQ17rwNormal read/write0x0Signals the clearing of the external global exclusive monitor request, and sends a WFE wake-up event to all CPU cores
L2FLUSHREQ16rwNormal read/write0x0L2 hardware flush request
CPUPWRDWNREQ 3:0rwNormal read/write0Request to power down CPU<n> island