PWRCTL (DDRC) Register Description
| Register Name | PWRCTL |
|---|---|
| Offset Address | 0x0000000030 |
| Absolute Address | 0x00FD070030 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Low Power Control Register |
This register is dynamic. Dynamic registers can be written at any time during operation.
PWRCTL (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| stay_in_selfref | 6 | rwNormal read/write | 0x0 | Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state for LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 0 - Allow transition from Self refresh state |
| selfref_sw | 5 | rwNormal read/write | 0x0 | A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Software Exit from Self Refresh |
| mpsm_en | 4 | rwNormal read/write | 0x0 | When this is 1, the DDRC puts the SDRAM into maximum power saving mode when the transaction store is empty. This register must be reset to 0 to bring DDRC out of maximum power saving mode. For non-DDR4, this register should not be set to 1. FOR PERFORMANCE ONLY. |
| en_dfi_dram_clk_disable | 3 | rwNormal read/write | 0x0 | Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR3, can only be asserted in Self Refresh. In DDR4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In LPDDR3, can be asserted in following: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asserted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop) |
| deeppowerdown_en | 2 | rwNormal read/write | 0x0 | When this is 1, DDRC puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be reset to 0 to bring DDRC out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down exit. For non-LPDDR3, this register should not be set to 1. FOR PERFORMANCE ONLY. |
| powerdown_en | 1 | rwNormal read/write | 0x0 | If true then the DDRC goes into power-down after a programmable number of cycles maximum idle clocks before power down (PWRTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation. |
| selfref_en | 0 | rwNormal read/write | 0x0 | If true then the DDRC puts the SDRAM into Self Refresh after a programmable number of cycles maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32). This register bit may be re-programmed during the course of normal operation. |