PWRTMG (DDRC) Register Description
| Register Name | PWRTMG |
|---|---|
| Offset Address | 0x0000000034 |
| Absolute Address | 0x00FD070034 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00402010 |
| Description | Low Power Timing Register |
This register is static. Static registers can only be written when the controller is in reset.
PWRTMG (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| selfref_to_x32 | 23:16 | rwNormal read/write | 0x40 | After this many clocks of NOP or deselect the DDRC automatically puts the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. |
| t_dpd_x4096 | 15:8 | rwNormal read/write | 0x20 | Minimum deep power-down time. For LPDDR3, value from the JEDEC specification is 500us. Unit: Multiples of 4096 clocks. FOR PERFORMANCE ONLY. |
| powerdown_to_x32 | 4:0 | rwNormal read/write | 0x10 | After this many clocks of NOP or deselect the DDRC automatically puts the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. |