Performance_Monitor_Control_Register (CCI400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

Performance_Monitor_Control_Register (CCI400) Register Description

Register NamePerformance_Monitor_Control_Register
Offset Address0x0000000100
Absolute Address 0x00FD6E0100 (CCI_GPV)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00002000
DescriptionPerformance_Monitor_Control_Register

Performance_Monitor_Control_Register (CCI400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PMU_Count_Num15:11roRead-only0x4Number of PMU counters available
DP 5rwNormal read/write0x0Disables cycle counter, CCNT, if non-invasive debug is prohibited
EX 4rwNormal read/write0x0Enable export of the events to the event bus, EVNTBUS, for an external monitoring block to trace events.
CCD 3rwNormal read/write0x0Cycle count divider
CCR 2woWrite-only0x0Reset cycle counter
RST 1woWrite-only0x0Reset all performance counters, not including CCNT
CEN 0rwNormal read/write0x0Enable all counters