QOS_CTRL (DDR_QOS_CTRL) Register Description
| Register Name | QOS_CTRL |
|---|---|
| Offset Address | 0x0000000004 |
| Absolute Address | 0x00FD090004 (DDR_QOS_CTRL) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00400000 |
| Description | Set Port Type Register |
QOS_CTRL (DDR_QOS_CTRL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:23 | razRead as zero | 0x0 | Reserved for future use |
| APB_ERR_RES | 22 | rwNormal read/write | 0x1 | When an APB (register) access occurs to an unimplemented space (there is no register at that location), the resulting pslverr will be: 0: pslverr = 1b0 1: pslverr = 1b1 There is also a maskable interrupt , "INV_APB" that could be asserted, independent of what option is selected here. |
| PORT5_WR_CTRL | 21 | rwNormal read/write | 0x0 | Port 5 QoS throttle Control on Write channel 0 - Disable 1 - Enable |
| PORT5_HPR_CTRL | 20 | rwNormal read/write | 0x0 | Port 5 QoS throttle Control on Read HPR channel 0 - Disable 1 - Enable |
| PORT5_LPR_CTRL | 19 | rwNormal read/write | 0x0 | Port 5 QoS throttle Control on Read LPR channel 0 - Disable 1 - Enable |
| PORT4_WR_CTRL | 18 | rwNormal read/write | 0x0 | Port 4 QoS throttle Control on Write channel 0 - Disable 1 - Enable |
| PORT4_HPR_CTRL | 17 | rwNormal read/write | 0x0 | Port 4 QoS throttle Control on Read HPR channel 0 - Disable 1 - Enable |
| PORT4_LPR_CTRL | 16 | rwNormal read/write | 0x0 | Port 4 QoS throttle Control on Read LPR channel 0 - Disable 1 - Enable |
| PORT3_WR_CTRL | 15 | rwNormal read/write | 0x0 | Port 3 QoS throttle Control on Write channel 0 - Disable 1 - Enable |
| PORT3_HPR_CTRL | 14 | rwNormal read/write | 0x0 | Port 3 QoS throttle Control on Read HPR channel 0 - Disable 1 - Enable |
| PORT3_LPR_CTRL | 13 | rwNormal read/write | 0x0 | Port 3 QoS throttle Control on Read LPR channel 0 - Disable 1 - Enable |
| PORT2_WR_CTRL | 12 | rwNormal read/write | 0x0 | Port 2 QoS throttle Control on Write channel 0 - Disable 1 - Enable |
| PORT2B_HPR_CTRL | 11 | rwNormal read/write | 0x0 | Port 2 Blue Queue QoS throttle Control on Read HPR channel 0 - Disable 1 - Enable |
| PORT2B_LPR_CTRL | 10 | rwNormal read/write | 0x0 | Port 2 Blue Queue throttle Control on Read LPR channel 0 - Disable 1 - Enable |
| PORT2R_HPR_CTRL | 9 | rwNormal read/write | 0x0 | Port 2 Red Queue QoS throttle Control on Read HPR channel 0 - Disable 1 - Enable |
| PORT2R_LPR_CTRL | 8 | rwNormal read/write | 0x0 | Port 2 Red Queue QoS throttle Control on Read LPR channel 0 - Disable 1 - Enable |
| PORT1_WR_CTRL | 7 | rwNormal read/write | 0x0 | Port 1 QoS throttle Control on Write channel 0 - Disable 1 - Enable |
| PORT1B_HPR_CTRL | 6 | rwNormal read/write | 0x0 | Port 1 Blue Queue throttle QoS Control on Read HPR channel 0 - Disable 1 - Enable |
| PORT1B_LPR_CTRL | 5 | rwNormal read/write | 0x0 | Port 1 Blue Queue throttle Control on Read LPR channel 0 - Disable 1 - Enable |
| PORT1R_HPR_CTRL | 4 | rwNormal read/write | 0x0 | Port 1 Red Queue QoS throttle Control on Read HPR channel 0 - Disable 1 - Enable |
| PORT1R_LPR_CTRL | 3 | rwNormal read/write | 0x0 | Port 1 Red Queue QoS throttle Control on Read LPR channel 0 - Disable 1 - Enable |
| PORT0_WR_CTRL | 2 | rwNormal read/write | 0x0 | Port 0 QoS throttle Control on Write channel 0 - Disable 1 - Enable |
| PORT0_HPR_CTRL | 1 | rwNormal read/write | 0x0 | Port 0 QoS throttle Control on Read HPR channel 0 - Disable 1 - Enable |
| PORT0_LPR_CTRL | 0 | rwNormal read/write | 0x0 | Port 0 QoS throttle Control on Read LPR channel 0 - Disable 1 - Enable |