QOS_IRQ_ENABLE (DDR_QOS_CTRL) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

QOS_IRQ_ENABLE (DDR_QOS_CTRL) Register Description

Register Name	QOS_IRQ_ENABLE
Offset Address	0x0000000208
Absolute Address	0x00FD090208 (DDR_QOS_CTRL)
Width	32
Type	mixedMixed types. See bit-field details.
Reset Value	0x00000000
Description	Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)

QOS_IRQ_ENABLE (DDR_QOS_CTRL) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
Reserved	31:11	razRead as zero	0x0	Reserved for future use
DDRC_WR_POISON	10	woWrite-only	0x0	See QOS_IRQ_STATUS register for details
DDRC_RD_POISON	9	woWrite-only	0x0	See QOS_IRQ_STATUS register for details
MRR_DATA_VALID	8	woWrite-only	0x0	See QOS_IRQ_STATUS register for details
PC_COPY_DONE	7	woWrite-only	0x0	See QOS_IRQ_STATUS register for details
DFI_ALT_ERR	6	woWrite-only	0x0	See QOS_IRQ_STATUS register for details
DFI_ALT_ERR_MAX	5	woWrite-only	0x0	See QOS_IRQ_STATUS register for details
DFI_ALT_ERR_FTL	4	woWrite-only	0x0	See QOS_IRQ_STATUS register for details
DFI_INIT_COMP	3	woWrite-only	0x0	See QOS_IRQ_STATUS register for details
DDRECC_UNCRERR	2	woWrite-only	0x0	See QOS_IRQ_STATUS register for details
DDRECC_CORERR	1	woWrite-only	0x0	See QOS_IRQ_STATUS register for details
INV_APB	0	woWrite-only	0x0	See QOS_IRQ_STATUS register for details