Field Name | Bits | Type | Reset Value | Description |
Reserved | 31:11 | razRead as zero | 0x0 | Reserved for future use |
DDRC_WR_POISON | 10 | roRead-only | 0x1 | See QOS_IRQ_STATUS register for details |
DDRC_RD_POISON | 9 | roRead-only | 0x1 | See QOS_IRQ_STATUS register for details |
MRR_DATA_VALID | 8 | roRead-only | 0x1 | See QOS_IRQ_STATUS register for details |
PC_COPY_DONE | 7 | roRead-only | 0x1 | See QOS_IRQ_STATUS register for details |
DFI_ALT_ERR | 6 | roRead-only | 0x1 | See QOS_IRQ_STATUS register for details |
DFI_ALT_ERR_MAX | 5 | roRead-only | 0x1 | See QOS_IRQ_STATUS register for details |
DFI_ALT_ERR_FTL | 4 | roRead-only | 0x1 | See QOS_IRQ_STATUS register for details |
DFI_INIT_COMP | 3 | roRead-only | 0x1 | See QOS_IRQ_STATUS register for details |
DDRECC_UNCRERR | 2 | roRead-only | 0x1 | See QOS_IRQ_STATUS register for details |
DDRECC_CORERR | 1 | roRead-only | 0x1 | See QOS_IRQ_STATUS register for details |
INV_APB | 0 | roRead-only | 0x1 | See QOS_IRQ_STATUS register for details |