QOS_IRQ_MASK (DDR_QOS_CTRL) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

QOS_IRQ_MASK (DDR_QOS_CTRL) Register Description

Register NameQOS_IRQ_MASK
Offset Address0x0000000204
Absolute Address 0x00FD090204 (DDR_QOS_CTRL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x000007FF
DescriptionInterrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER.

QOS_IRQ_MASK (DDR_QOS_CTRL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:11razRead as zero0x0Reserved for future use
DDRC_WR_POISON10roRead-only0x1See QOS_IRQ_STATUS register for details
DDRC_RD_POISON 9roRead-only0x1See QOS_IRQ_STATUS register for details
MRR_DATA_VALID 8roRead-only0x1See QOS_IRQ_STATUS register for details
PC_COPY_DONE 7roRead-only0x1See QOS_IRQ_STATUS register for details
DFI_ALT_ERR 6roRead-only0x1See QOS_IRQ_STATUS register for details
DFI_ALT_ERR_MAX 5roRead-only0x1See QOS_IRQ_STATUS register for details
DFI_ALT_ERR_FTL 4roRead-only0x1See QOS_IRQ_STATUS register for details
DFI_INIT_COMP 3roRead-only0x1See QOS_IRQ_STATUS register for details
DDRECC_UNCRERR 2roRead-only0x1See QOS_IRQ_STATUS register for details
DDRECC_CORERR 1roRead-only0x1See QOS_IRQ_STATUS register for details
INV_APB 0roRead-only0x1See QOS_IRQ_STATUS register for details