QOS_IRQ_STATUS (DDR_QOS_CTRL) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

QOS_IRQ_STATUS (DDR_QOS_CTRL) Register Description

Register NameQOS_IRQ_STATUS
Offset Address0x0000000200
Absolute Address 0x00FD090200 (DDR_QOS_CTRL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionInterrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.

QOS_IRQ_STATUS (DDR_QOS_CTRL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:11razRead as zero0x0Reserved for future use
DDRC_WR_POISON10wtcReadable, write a 1 to clear0x0Write poison interrupt status from DDRC. ORd of Write poison interrupt from all XPIs. Program DDRC.POISONCFG.wr_poison_intr_en to enables/disables interrupts for write transaction poisoning. Use DDRC.POISONSTAT status register to find which XPI cause transaction poisoning.
DDRC_RD_POISON 9wtcReadable, write a 1 to clear0x0Read poison interrupt status from DDRC. ORd of Read poison from all XPIs. Program DDRC.POISONCFG.rd_poison_intr_en to enables/disables interrupts for read transaction poisoning. Use DDRC.POISONSTAT status register to find which XPI cause transaction poisoning.
MRR_DATA_VALID 8wtcReadable, write a 1 to clear0x0When asserted high, indicates that data on DDR_QOS_CTRL.DDRC_MRR_DATA* is valid.
PC_COPY_DONE 7wtcReadable, write a 1 to clear0x0Generate interrupt when copy happened in Performance Counters
DFI_ALT_ERR 6wtcReadable, write a 1 to clear0x0This interrupt is asserted when a parity or CRC error is detected on the DFI interface.
DFI_ALT_ERR_MAX 5wtcReadable, write a 1 to clear0x0This interrupt is asserted when the DDRC.CRCPARSTAT.dfi_alert_err_cnt reaches it maximum value, and the interrupt is enabled by DDRC.CRCPARCTL0.dfi_alert_err_int_en.
DFI_ALT_ERR_FTL 4wtcReadable, write a 1 to clear0x0This interrupt is asserted when a parity error due to MRS is detected on the DFI interface.
DFI_INIT_COMP 3wtcReadable, write a 1 to clear0x0PHY Initialization Complete Indication
DDRECC_UNCRERR 2wtcReadable, write a 1 to clear0x0When an uncorrectable ECC error is detected by DDRC
DDRECC_CORERR 1wtcReadable, write a 1 to clear0x0When a correctable ECC error is detected by DDRC
INV_APB 0wtcReadable, write a 1 to clear0x0APB (register) access occurs to an unimplemented space