Qos_Control_Register_S0 (CCI400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

Qos_Control_Register_S0 (CCI400) Register Description

Register NameQos_Control_Register_S0
Offset Address0x000000110C
Absolute Address 0x00FD6E110C (CCI_GPV)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionQos_Control_Register_S0

Qos_Control_Register_S0 (CCI400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
QoS_regulation_disabled31roRead-only0x0High if QoS regulation is disabled in slave interface S0
Bandwidth_regulation_mode21rwNormal read/write0x0Select between normal or quiesce high mode of bandwidth regulation for slave interface S0
ARQOS_regulation_mode20rwNormal read/write0x0Select between bandwidth or latency mode of ARQOS regulation for slave interface S0
AWQOS_regulation_mode16rwNormal read/write0x0Select between bandwidth or latency mode of AWQOS regulation for slave interface S0
AR_OT_regulation 3rwNormal read/write0x0Enable regulation of outstanding read transactions for slave interface S0
AW_OT_regulation 2rwNormal read/write0x0Enable regulation of outstanding write transactions for slave interface S0
ARQOS_regulation 1rwNormal read/write0x0Enable QoS value regulation on reads for slave interface S0
AWQOS_regulation 0rwNormal read/write0x0Enable QoS value regulation on writes for slave interface S0