R00_CONFIG (XMPU_FPD) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

R00_CONFIG (XMPU_FPD) Register Description

Register NameR00_CONFIG
Offset Address0x000000010C
Absolute Address 0x00FD5D010C (FPD_XMPU_CFG)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000008
DescriptionRegion 0 Configuration.

If a transaction address is with an enabled Regions start and end addresses, then the [WrAllowed] / [RdAllowed] condition is checked. If the transaction R/W type is allowed, then the security check is performed. When more than one address region includes the transaction address (regions overlap), the Region with the higher number takes precedence.

R00_CONFIG (XMPU_FPD) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:5roRead-only0x0reserved
NSCheckType 4rwNormal read/write0x0Non-secure Region Check Type. Secure masters may or may not be allowed to access Non-Secure (NS) memory regions.
0: relaxed checking; secure requests may access a non-secure (NS) region.
1: strict checking; secure requests may only access a secure region.
A non-secure access request can only access non-secure regions regardless of bit setting.
RegionNS 3rwNormal read/write0x1Select security level of region:
0: secure.
1: non-secure (NS).
WrAllowed 2rwNormal read/write0x0Allow writes to region:
0: not allowed; write transaction poisoned.
1: allowed.
RdAllowed 1rwNormal read/write0x0Allow reads within region:
0: not allowed; read transaction poisoned.
1: allowed.
Enable 0rwNormal read/write0x0Enable region:
0: disabled.
1: enabled.