R00_MASTER (XMPU_DDR) Register Description
| Register Name | R00_MASTER |
|---|---|
| Offset Address | 0x0000000108 |
| Absolute Address |
0x00FD000108 (DDR_XMPU0_CFG) 0x00FD010108 (DDR_XMPU1_CFG) 0x00FD020108 (DDR_XMPU2_CFG) 0x00FD030108 (DDR_XMPU3_CFG) 0x00FD040108 (DDR_XMPU4_CFG) 0x00FD050108 (DDR_XMPU5_CFG) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Region 0 Master ID. |
The AXI_MasterID from the requester is compared with all the configured regions. The mask is applied to the incoming MasterID and all of the Rxx_MASTER.ID bit fields. AXI_MasterID & [MASK] == [ID] & [MASK]: False: transaction is poisoned. True: transaction is forwarded downstream.
R00_MASTER (XMPU_DDR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:26 | roRead-only | 0x0 | reserved |
| MASK | 25:16 | rwNormal read/write | 0x0 | Master_ID mask. |
| Reserved | 15:10 | roRead-only | 0x0 | reserved |
| ID | 9:0 | rwNormal read/write | 0x0 | Master_ID value. |