R02_CONFIG (XMPU_DDR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

R02_CONFIG (XMPU_DDR) Register Description

Register NameR02_CONFIG
Offset Address0x000000012C
Absolute Address 0x00FD00012C (DDR_XMPU0_CFG)
0x00FD01012C (DDR_XMPU1_CFG)
0x00FD02012C (DDR_XMPU2_CFG)
0x00FD03012C (DDR_XMPU3_CFG)
0x00FD04012C (DDR_XMPU4_CFG)
0x00FD05012C (DDR_XMPU5_CFG)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000008
DescriptionRegion 2 Configuration.

Refer to R00_CONFIG for more information.

R02_CONFIG (XMPU_DDR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:5roRead-only0x0reserved
NSCheckType 4rwNormal read/write0x0Non-secure Region Check Type. Secure masters may or may not be allowed to access Non-Secure (NS) memory regions.
0: relaxed checking; secure requests may access a non-secure (NS) region.
1: strict checking; secure requests may only access a secure region.
RegionNS 3rwNormal read/write0x1Select security level of region:
0: secure.
1: non-secure (NS).
WrAllowed 2rwNormal read/write0x0Allow writes to region:
0: not allowed; transaction poisoned.
1: allowed.
RdAllowed 1rwNormal read/write0x0Allow reads within region:
0: not allowed; transaction poisoned.
1: allowed.
Enable 0rwNormal read/write0x0Enable region:
0: disabled.
1: enabled.