R04_MASTER (XMPU_DDR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

R04_MASTER (XMPU_DDR) Register Description

Register NameR04_MASTER
Offset Address0x0000000148
Absolute Address 0x00FD000148 (DDR_XMPU0_CFG)
0x00FD010148 (DDR_XMPU1_CFG)
0x00FD020148 (DDR_XMPU2_CFG)
0x00FD030148 (DDR_XMPU3_CFG)
0x00FD040148 (DDR_XMPU4_CFG)
0x00FD050148 (DDR_XMPU5_CFG)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegion 4 Master ID.

Refer to R00_MASTER for more information.

R04_MASTER (XMPU_DDR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:26roRead-only0x0reserved
MASK25:16rwNormal read/write0x0Master_ID mask.
Reserved15:10roRead-only0x0reserved
ID 9:0rwNormal read/write0x0Master_ID value.