R12_END (XMPU_DDR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

R12_END (XMPU_DDR) Register Description

Register NameR12_END
Offset Address0x00000001C4
Absolute Address 0x00FD0001C4 (DDR_XMPU0_CFG)
0x00FD0101C4 (DDR_XMPU1_CFG)
0x00FD0201C4 (DDR_XMPU2_CFG)
0x00FD0301C4 (DDR_XMPU3_CFG)
0x00FD0401C4 (DDR_XMPU4_CFG)
0x00FD0501C4 (DDR_XMPU5_CFG)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegion 12 End Address.

Refer to R00_END for more information.

R12_END (XMPU_DDR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:28roRead-only0x0reserved
ADDR27:0rwNormal read/write0x0Bits [27:8] correspond to address bits [39:20].
Bits [7:0] are reserved.