RDIMMGCR0 (DDR_PHY) Register Description
| Register Name | RDIMMGCR0 |
|---|---|
| Offset Address | 0x0000000140 |
| Absolute Address | 0x00FD080140 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x08400020 |
| Description | RDIMM General Configuration Register 0 |
RDIMMGCR0 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| QCSEN | 30 | rwNormal read/write | 0x0 | RDMIMM Quad CS Enable: Enables, if set, the Quad CS mode for the RDIMM registering buffer chip. This register bit controls the buffer chip QCSEN# signal. |
| Reserved | 29:28 | roRead-only | 0x0 | Return zeroes on reads. |
| RDIMMIOM | 27 | rwNormal read/write | 0x1 | RDIMM Outputs I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for QCSEN# and MIRROR pins. |
| Reserved | 26:24 | roRead-only | 0x0 | Return zeroes on reads. |
| ERROUTOE | 23 | rwNormal read/write | 0x0 | ERROUT# Output Enable: Enables, when set, the output driver on the I/O for ERROUT# pin. |
| ERROUTIOM | 22 | rwNormal read/write | 0x1 | ERROUT# I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for ERROUT# pin. |
| ERROUTPDR | 21 | rwNormal read/write | 0x0 | ERROUT# Power Down Receiver: Powers down, when set, the input receiver on the I/O for ERROUT# pin. |
| Reserved | 20 | roRead-only | 0x0 | Return zeroes on reads. |
| ERROUTODT | 19 | rwNormal read/write | 0x0 | ERROUT# On-Die Termination: Enables, when set, the on-die termination on the I/O for ERROUT# pin. |
| PARINIOM | 17 | rwNormal read/write | 0x0 | PAR_IN I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for PAR_IN pin. |
| Reserved | 16:8 | roRead-only | 0x0 | Return zeroes on reads. |
| RNKMRREN_RSVD | 7:6 | roRead-only | 0x0 | Return zeroes on reads. |
| RNKMRREN | 5:4 | rwNormal read/write | 0x2 | Rank Mirror Enable: Specifies the ranks that are mirrored. Bit 0 controls rank 0, bit 1 controls rank 1, etc. Setting the bit to 1b1 enables the address mirroring for that rank and setting it to 1b0 disables the mirroring for that rank. This is valid for RDIMM and UDIMM. Default Mirroring on ODD rank is enabled. |
| Reserved | 3 | roRead-only | 0x0 | Return zeroes on reads. |
| SOPERR | 2 | rwNormal read/write | 0x0 | Stop on Parity Error: Stops PUB transactions when RDIMM parity error is asserted. This bit should be programmed to 1'b0 when the PUB is executing BIST in loopback mode. |
| ERRNOREG | 1 | rwNormal read/write | 0x0 | Parity Error No Registering: Indicates, if set, that parity error signal from the RDIMM should be passed to the DFI controller without any synchronization or registering. Otherwise, the error signal is synchronized. |
| RDIMM | 0 | rwNormal read/write | 0x0 | Registered DIMM: If set, indicates that a registered DIMM is used. For PUB internal SDRAM transactions, the PUB enforces that accesses adhere to RDIMM buffer chip. Transactions generated by the controller make adjustments to WL/RL when using a registered DIMM. Note: The NOSRA bit in the 'DRAM Configuration Register (DCR)'must be set to '1' if using the standard RDIMM buffer chip so that normal DRAM accesses do not assert multiple chip select bits at the same time. |