RDIMMGCR1 (DDR_PHY) Register Description
| Register Name | RDIMMGCR1 |
|---|---|
| Offset Address | 0x0000000144 |
| Absolute Address | 0x00FD080144 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000C80 |
| Description | RDIMM General Configuration Register 1 |
RDIMMGCR1 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:29 | roRead-only | 0x0 | Return zeroes on reads. |
| A17BID | 28 | rwNormal read/write | 0x0 | Address [17] B-side Inversion Disable |
| Reserved | 27 | roRead-only | 0x0 | Return zeroes on reads. |
| tBCMRD_L2 | 26:24 | rwNormal read/write | 0x0 | Command word to command word programming delay: Number of DRAM clock cycles between two RDIMM buffer chip command programming accesses for RC0F and RC0D. The value used for tBCMRD_L2 is 32 plus the value programmed in these bits, i.e. tBCMRD_L2 value ranges from 32 to 39. This parameter corresponds to the buffer chip tMRD_L2parameter. |
| Reserved | 23 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| tBCMRD_L | 22:20 | rwNormal read/write | 0x0 | Command word to command word programming delay: Number of DRAM clock cycles between two RDIMM buffer chip command programming accesses for RC03, RC04, RC05 and RC0B. The value used for tBCMRD_L is 16 plus the value programmed in these bits, i.e. tBCMRD_L value ranges from 16 to 23. This parameter corresponds to the buffer chip tMRD_L parameter. |
| Reserved | 19 | roRead-only | 0x0 | Return zeroes on reads. |
| tBCMRD | 18:16 | rwNormal read/write | 0x0 | Command word to command word programming delay: Number of DRAM clock cycles between two RDIMM buffer chip command programming accesses. The value used for tBCMRD is 8 plus the value programmed in these bits, i.e. tBCMRD value ranges from 8 to 15. This parameter corresponds to the buffer chip tMRD parameter. The minimum value programmed for this register should be equivalent to tMRD. |
| Reserved | 15:14 | roRead-only | 0x0 | Return zeroes on reads. |
| tBCSTAB | 13:0 | rwNormal read/write | 0xC80 | Stabilization time: Number of DRAM clock cycles for the RDIMM buffer chip to stabilize. This parameter corresponds to the buffer chip tSTAB parameter. Default value is in decimal format and corresponds to 6us at 533MHz. |