RDIMMGCR2 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

RDIMMGCR2 (DDR_PHY) Register Description

Register NameRDIMMGCR2
Offset Address0x0000000148
Absolute Address 0x00FD080148 (DDR_PHY)
Width32
TyperwNormal read/write
Reset Value0x03FFFFBF
DescriptionRDIMM General Configuration Register 2

RDIMMGCR2 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CRINIT31:0rwNormal read/write0x3FFFFBFControl Registers Initialization Enable: Indicates which RDIMM buffer
chip control registers (RC0 to RC15) should be initialized (written)
when the PUB is triggered to initialize the buffer chip. A setting of '1'on CRINIT[n] bit means that CRn should be written during
initialization.