| Register Name | Offset Address | Width | Type | Reset Value | Description |
|---|
| IDFILTER0 | 0x0000000000 | 32 | rwNormal read/write | 0x00000000 | Allows the setting of ID filter for Master 0. |
| IDFILTER1 | 0x0000000004 | 32 | rwNormal read/write | 0x00000000 | Allows the setting of ID filter for Master 1. |
| ITATBCTR1 | 0x0000000EF8 | 32 | roRead-only | 0x00000000 | Returns the value of the ATREADYM0, ATREADYM1 and ATVALIDS inputs in integration mode. |
| ITATBCTR0 | 0x0000000EFC | 32 | woWrite-only | 0x00000000 | Controls the value of the ATVALIDM0, ATVALIDM1 and ATREADYS outputs in integration mode. |
| ITCTRL | 0x0000000F00 | 32 | rwNormal read/write | 0x00000000 | Used to enable topology detection. See the CoreSight Architecture Specification for more information. This register enables the component to switch from a functional mode, the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving. Note: When a device has been in integration mode, it might not function with the original behavior. After performing integration or topology detection, you must reset the system to ensure correct behavior of CoreSight and other connected system components that are affected by the integration or topology detection. |
| CLAIMSET | 0x0000000FA0 | 32 | rwNormal read/write | 0x00000000 | This is used in conjunction with Claim Tag Clear Register, CLAIMCLR. This register forms one half of the Claim Tag value. This location allows individual bits to be set, write, and returns the number of bits that can be set, read. |
| CLAIMCLR | 0x0000000FA4 | 32 | rwNormal read/write | 0x00000000 | This register is used in conjunction with Claim Tag Set Register, CLAIMSET. This register forms one half of the Claim Tag value. This location enables individual bits to be cleared, write, and returns the current Claim Tag value, read. |
| LAR | 0x0000000FB0 | 32 | woWrite-only | 0x00000000 | This is used to enable write access to device registers. |
| LSR | 0x0000000FB4 | 32 | roRead-only | 0x00000000 | This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. This register must always be present although there might not be any lock access control mechanism. The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. For most components this covers all registers except for the Lock Access Register, 0xFB0. |
| AUTHSTATUS | 0x0000000FB8 | 32 | roRead-only | 0x00000000 | Reports the required security level and current status of those enables. Where functionality changes on a given security level then this change in status must be reported in this register |
| DEVID | 0x0000000FC8 | 32 | roRead-only | 0x00000000 | Indicates the capabilities of the CoreSight Replicator. |
| DEVTYPE | 0x0000000FCC | 32 | roRead-only | 0x00000000 | Provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. |
| PIDR4 | 0x0000000FD0 | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains part of the designer identity and the memory footprint indicator. |
| PIDR5 | 0x0000000FD4 | 32 | rwNormal read/write | 0x00000000 | Reserved |
| PIDR6 | 0x0000000FD8 | 32 | rwNormal read/write | 0x00000000 | Reserved |
| PIDR7 | 0x0000000FDC | 32 | rwNormal read/write | 0x00000000 | Reserved |
| PIDR0 | 0x0000000FE0 | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains part of the designer specific part number. |
| PIDR1 | 0x0000000FE4 | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains part of the designer specific part number and part of the designer identity. |
| PIDR2 | 0x0000000FE8 | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains part of the designer identity and the product revision. |
| PIDR3 | 0x0000000FEC | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains the RevAnd and Customer Modified fields. |
| CIDR0 | 0x0000000FF0 | 32 | roRead-only | 0x00000000 | A component identification register, that indicates that the identification registers are present. |
| CIDR1 | 0x0000000FF4 | 32 | roRead-only | 0x00000000 | A component identification register, that indicates that the identification registers are present. This register also indicates the component class. |
| CIDR2 | 0x0000000FF8 | 32 | roRead-only | 0x00000000 | A component identification register, that indicates that the identification registers are present. |
| CIDR3 | 0x0000000FFC | 32 | roRead-only | 0x00000000 | A component identification register, that indicates that the identification registers are present. |