REQ_SWRST_STATUS (PMU_GLOBAL) Register Description
| Register Name | REQ_SWRST_STATUS |
|---|---|
| Offset Address | 0x0000000410 |
| Absolute Address | 0x00FFD80410 (PMU_GLOBAL) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Reset Request; Interrupt Status and Clear. |
Status and clear of Reset Requests. Read: 0: no request. 1: reset request active. Write: 0: no effect. 1: clear the bit to 0.
REQ_SWRST_STATUS (PMU_GLOBAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PL | 31 | wtcReadable, write a 1 to clear | 0x0 | Programmable Logic, PL reset request. |
| FP | 30 | wtcReadable, write a 1 to clear | 0x0 | Full Power Domain, FPD reset request. System-level reset ensures FPD transactions are flushed and the FPD is blocked before the reset. |
| LP | 29 | wtcReadable, write a 1 to clear | 0x0 | Low Power Domain, LPD reset request. |
| PS_ONLY | 28 | wtcReadable, write a 1 to clear | 0x0 | PS-only reset request. System-level reset ensures the PS transactions are flushed and PS is blocked before the reset. First set PMU_GLOBAL.PS_CTRL [PROG_GATE] = 1 to block the reset to the PL. |
| IOU | 27 | wtcReadable, write a 1 to clear | 0x0 | IOP reset request. |
| Reserved | 26 | roRead-only | 0x0 | reserved |
| USB1 | 25 | wtcReadable, write a 1 to clear | 0x0 | USB1 reset request. |
| USB0 | 24 | wtcReadable, write a 1 to clear | 0x0 | USB0 reset request. |
| GEM3 | 23 | wtcReadable, write a 1 to clear | 0x0 | GEM3 reset request. |
| GEM2 | 22 | wtcReadable, write a 1 to clear | 0x0 | GEM2 reset request. |
| GEM1 | 21 | wtcReadable, write a 1 to clear | 0x0 | GEM1 reset request. |
| GEM0 | 20 | wtcReadable, write a 1 to clear | 0x0 | GEM0 reset request. |
| Reserved | 19 | roRead-only | 0x0 | reserved |
| RPU | 18 | wtcReadable, write a 1 to clear | 0x0 | RPU Lockstep reset request. System-level reset ensures RPU transactions are flushed and the RPU master is blocked before the reset. |
| R5_1 | 17 | wtcReadable, write a 1 to clear | 0x0 | RPU1 reset request. |
| R5_0 | 16 | wtcReadable, write a 1 to clear | 0x0 | RPU0 reset request. |
| Reserved | 15:13 | roRead-only | 0x0 | reserved |
| Display_Port | 12 | wtcReadable, write a 1 to clear | 0x0 | Display Port. |
| Reserved | 11 | roRead-only | 0x0 | reserved |
| SATA | 10 | wtcReadable, write a 1 to clear | 0x0 | SATA reset request. |
| PCIe | 9 | wtcReadable, write a 1 to clear | 0x0 | PCIe reset request. |
| GPU | 8 | wtcReadable, write a 1 to clear | 0x0 | Both GPU Pixel Processors reset request. |
| PP1 | 7 | wtcReadable, write a 1 to clear | 0x0 | GPU Pixel Processor 1 reset request. |
| PP0 | 6 | wtcReadable, write a 1 to clear | 0x0 | GPU Pixel Processor 0 reset request. |
| Reserved | 5 | roRead-only | 0x0 | reserved |
| APU | 4 | wtcReadable, write a 1 to clear | 0x0 | All APU processors reset request |
| ACPU3 | 3 | wtcReadable, write a 1 to clear | 0x0 | APU core 3, reset request. |
| ACPU2 | 2 | wtcReadable, write a 1 to clear | 0x0 | APU core 2, reset request. |
| ACPU1 | 1 | wtcReadable, write a 1 to clear | 0x0 | APU core 1, reset request. |
| ACPU0 | 0 | wtcReadable, write a 1 to clear | 0x0 | APU core 0, reset request. |