RFSHCTL0_SHADOW (DDRC) Register Description
| Register Name | RFSHCTL0_SHADOW |
|---|---|
| Offset Address | 0x0000002050 |
| Absolute Address | 0x00FD072050 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00210000 |
| Description | Refresh Control Shadow Register 0 |
All register fields are dynamic - refresh related, unless described otherwise in the register field description. Refresh related dynamic registers can be written at any time during operation, but to update them the following must be done: * Change the refresh associated register as desired. * After the changed register is known stable, toggle the RFSHCTL3.refresh_update_level signal.
RFSHCTL0_SHADOW (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| refresh_margin | 23:20 | rwNormal read/write | 0x2 | Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR3, internally used t_rfc_nom_x32 may be equal to RFSHTMG_SHADOW.t_rfc_nom_x32_shadow>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to RFSHTMG_SHADOW.t_rfc_nom_x32_shadow. Unit: Multiples of 32 clocks. |
| refresh_to_x32 | 16:12 | rwNormal read/write | 0x10 | If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0_SHADOW.refresh_burst_shadow+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0_SHADOW.refresh_to_x32_shadow and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the DDRC. FOR PERFORMANCE ONLY. |
| refresh_burst | 8:4 | rwNormal read/write | 0x0 | The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL0_SHADOW.refresh_burst_shadow slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For DDR3, the refresh is always per-rank and not per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care must be taken in the setting of RFSHCTL0_SHADOW.refresh_burst_shadow, to ensure that tRFCmax is not violated due to a PHY-initiated update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY-initiated update is complete. |
| per_bank_refresh | 2 | rwNormal read/write | 0x0 | - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is supported by all LPDDR3/LPDDR4 devices. Programming Mode: Static |