RFSHCTL1 (DDRC) Register Description
Register Name | RFSHCTL1 |
---|---|
Offset Address | 0x0000000054 |
Absolute Address | 0x00FD070054 (DDRC) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Refresh Control Register 1 |
This register is dynamic - refresh related. Refresh related dynamic registers can be written at any time during operation, but to update them the following must be done: * Change the refresh associated register as desired. * After the changed register is known stable, toggle the RFSHCTL3.refresh_update_level signal.
RFSHCTL1 (DDRC) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
refresh_timer1_start_value_x32 | 27:16 | rwNormal read/write | 0x0 | Refresh timer start for rank 1. This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. |
refresh_timer0_start_value_x32 | 11:0 | rwNormal read/write | 0x0 | Refresh timer start for rank 0. This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. |