RFSHCTL1 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

RFSHCTL1 (DDRC) Register Description

Register NameRFSHCTL1
Offset Address0x0000000054
Absolute Address 0x00FD070054 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionRefresh Control Register 1

This register is dynamic - refresh related. Refresh related dynamic registers can be written at any time during operation, but to update them the following must be done: * Change the refresh associated register as desired. * After the changed register is known stable, toggle the RFSHCTL3.refresh_update_level signal.

RFSHCTL1 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
refresh_timer1_start_value_x3227:16rwNormal read/write0x0Refresh timer start for rank 1. This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter.
Unit: Multiples of 32 clocks.
FOR PERFORMANCE ONLY.
refresh_timer0_start_value_x3211:0rwNormal read/write0x0Refresh timer start for rank 0. This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter.
Unit: Multiples of 32 clocks.
FOR PERFORMANCE ONLY.