RST_LPD_DBG (CRL_APB) Register Description
Register Name | RST_LPD_DBG |
Offset Address | 0x0000000240 |
Absolute Address |
0x00FF5E0240 (CRL_APB)
|
Width | 16 |
Type | rwNormal read/write |
Reset Value | 0x00000033 |
Description | Debug control for both the LPD and FPD. |
During a debug_reset, PMU will be told to reset this register. The register is reset only by a POR reset.
RST_LPD_DBG (CRL_APB) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
dbg_ack | 15 | rwNormal read/write | 0x0 | This is the ACK signal to the debug reset request from DAP controller. After debugger requests reset, it is up to the user to toggle this and the debug signals correctly. |
Reserved | 14:6 | rwNormal read/write | 0x0 | reserved |
rpu_dbg1_reset | 5 | rwNormal read/write | 0x1 | Resets the debug logic of R5_1 |
rpu_dbg0_reset | 4 | rwNormal read/write | 0x1 | Resets the debug logic of R5_0 |
Reserved | 3:2 | rwNormal read/write | 0x0 | reserved |
dbg_lpd_reset | 1 | rwNormal read/write | 0x1 | Resets the core sight debug component of the RPU: CTI, ETMs, CTM along with the soc_debug_lpd unit. |
dbg_fpd_reset | 0 | rwNormal read/write | 0x1 | Debug reset that goes to the FPD to reset part of the system debug logic. |