RST_LPD_DBG (CRL_APB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

RST_LPD_DBG (CRL_APB) Register Description

Register NameRST_LPD_DBG
Offset Address0x0000000240
Absolute Address 0x00FF5E0240 (CRL_APB)
Width16
TyperwNormal read/write
Reset Value0x00000033
DescriptionDebug control for both the LPD and FPD.

During a debug_reset, PMU will be told to reset this register. The register is reset only by a POR reset.

RST_LPD_DBG (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
dbg_ack15rwNormal read/write0x0This is the ACK signal to the debug reset request from DAP controller. After debugger requests reset, it is up to the user to toggle this and the debug signals correctly.
Reserved14:6rwNormal read/write0x0reserved
rpu_dbg1_reset 5rwNormal read/write0x1Resets the debug logic of R5_1
rpu_dbg0_reset 4rwNormal read/write0x1Resets the debug logic of R5_0
Reserved 3:2rwNormal read/write0x0reserved
dbg_lpd_reset 1rwNormal read/write0x1Resets the core sight debug component of the RPU: CTI, ETMs, CTM along with the soc_debug_lpd unit.
dbg_fpd_reset 0rwNormal read/write0x1Debug reset that goes to the FPD to reset part of the system debug logic.