RST_LPD_IOU2 (CRL_APB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2024-03-13

Revision

1.10

Each bit controls the reset of a system element.

Field Name	Bits	Type	Reset Value	Description
Reserved	31:21	rwNormal read/write	0x0	reserved
timestamp_reset	20	rwNormal read/write	0x1	TimeStamp controller
iou_cc_reset	19	rwNormal read/write	0x0	CC controller
gpio_reset	18	rwNormal read/write	0x1	GPIO controller
lpd_dma_reset	17	rwNormal read/write	0x1	LPD DMA controller Note: Field name reference: adma_reset
nand_reset	16	rwNormal read/write	0x1	NAND controller
swdt_reset	15	rwNormal read/write	0x1	CSU_SWDT controller
ttc3_reset	14	rwNormal read/write	0x1	TTC 3 controller
ttc2_reset	13	rwNormal read/write	0x1	TTC 2 controller
ttc1_reset	12	rwNormal read/write	0x1	TTC 1 controller
ttc0_reset	11	rwNormal read/write	0x1	TTC 0 controller
i2c1_reset	10	rwNormal read/write	0x1	I2C 1 controller
i2c0_reset	9	rwNormal read/write	0x1	I2C 0 controller
can1_reset	8	rwNormal read/write	0x1	CAN 1 controller
can0_reset	7	rwNormal read/write	0x1	CAN 0 controller
sdio1_reset	6	rwNormal read/write	0x1	SDIO 1 controller
sdio0_reset	5	rwNormal read/write	0x1	SDIO 0 controller
spi1_reset	4	rwNormal read/write	0x1	SPI 1 controller
spi0_reset	3	rwNormal read/write	0x1	SPI 0 controller
uart1_reset	2	rwNormal read/write	0x1	UART 1 controller
uart0_reset	1	rwNormal read/write	0x1	UART 0 controller
qspi_reset	0	rwNormal read/write	0x1	Quad-SPI controller