RST_LPD_TOP (CRL_APB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

RST_LPD_TOP (CRL_APB) Register Description

Register NameRST_LPD_TOP
Offset Address0x000000023C
Absolute Address 0x00FF5E023C (CRL_APB)
Width24
TyperwNormal read/write
Reset Value0x00188FDF
DescriptionSoftware Reset Control for LPD System Elements.

RST_LPD_TOP (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
fpd_reset23rwNormal read/write0x0Entire FPD.
Reserved22:21rwNormal read/write0x0reserved
lpd_swdt_reset20rwNormal read/write0x1LPD_SWDT Controller
s_axi_lpd_reset19rwNormal read/write0x1S_AXI_LPD Interface.
Reserved18rwNormal read/write0x0reserved
sysmon_reset17rwNormal read/write0x0PS System Monitor (PS SYSMON).
rtc_reset16rwNormal read/write0x0Real Time Clock (RTC).
apm_reset15rwNormal read/write0x1AXI Performance Monitors (APM).
ipi_reset14rwNormal read/write0x0InterProcessor Interrupt (IPI) registers.
Reserved13:12rwNormal read/write0x0reserved
usb1_apb_reset11rwNormal read/write0x1USB controller 1 reset for control registers.
usb0_apb_reset10rwNormal read/write0x1USB controller 0 reset for control registers.
usb1_hiberreset 9rwNormal read/write0x1USB controller 1 sleep circuit reset.
usb0_hiberreset 8rwNormal read/write0x1USB controller 0 sleep circuit reset.
usb1_corereset 7rwNormal read/write0x1USB controller 1 reset.
usb0_corereset 6rwNormal read/write0x1USB controller 0 reset.
Reserved 5rwNormal read/write0x0reserved
rpu_pge_reset 4rwNormal read/write0x1Entire RPU power island.
ocm_reset 3rwNormal read/write0x1OCM memory.
rpu_amba_reset 2rwNormal read/write0x1RPU misc reset.
rpu_r51_reset 1rwNormal read/write0x1RPU core 1.
rpu_r50_reset 0rwNormal read/write0x1RPU core 0.