SARBASE0 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SARBASE0 (DDRC) Register Description

Register NameSARBASE0
Offset Address0x0000000F04
Absolute Address 0x00FD070F04 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionSAR Base Address Register 0

This register is static. Static registers can only be written when the controller is in reset.

SARBASE0 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
base_addr 8:0rwNormal read/write0x0Base address for address region 0 specified as awaddr[39:x] and araddr[39:x]
where x is determined by the minimum block size, 2GB. x=log2(block size)=31.