SARSIZE0 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SARSIZE0 (DDRC) Register Description

Register NameSARSIZE0
Offset Address0x0000000F08
Absolute Address 0x00FD070F08 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionSAR Size Register 0

This register is static. Static registers can only be written when the controller is in reset.

SARSIZE0 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
nblocks 7:0rwNormal read/write0x0Number of blocks for address region 0.
This register determines the total size of the region in multiples of minimum block size, 2GB. The register value is encoded as number of blocks = nblocks + 1. For example, if register is programmed to 0, region will have 1 block.